1. Field of the Invention
The present invention relates to a failure analysis apparatus of semiconductor integrated circuits with a timing failure and the method thereof, and more specifically, to a failure analysis apparatus of semiconductor integrated circuits and the method thereof for easily identifying the failure occurring region in a short time.
2. Description of the Related Art
Recently, as the density of wiring in the semiconductor integrated circuit increases, the floating capacitance has increased. Consequently, in the wafer sorting process for inspecting electrical characteristics of wafers with elements formed, the wafer manufacturing yield may be lowered by occurrence of a failure in the timing system. The characteristics of the timing failure, in general, is to be a failure occurring in the specific test pattern among the inspections of electrical characteristics. That is, when the passivation film on the surface is removed, the wafer is not rejected due to the test pattern with which the same wafer is rejected in the previous electrical characteristic inspection but when the passivation film is formed on the wafer again, the wafer is judged to be rejected.
This kind of the timing failure is assumed to occur by changes of floating capacitance between metal wirings used in the semiconductor integrated circuits by the existence or non-existence of the passivation film on the wafer, which, in turn, causes variations to the time constant of the circuit.
In order to analyze the nonconforming wafer with the timing failure, a capacitance is formed in the region desired to be analyzed, and how the timing is deviated must be observed. This kind of an analysis method for nonconforming wafer will be described as follows. First of all, in the test pattern in which the wafer is rejected, an engineer who is familiar with the circuit technology presumes possible failure places of wiring in the pellet area. Then, using lasers and so forth, a hole is provided on the passivation film on the possible failure place, and a probe needle is set up on the wiring presumed to be failure. Then, while confirming the signal passing through this wiring by an oscilloscope and so forth, via the probe needle, the failure is investigated. If the failure portion is able to be identified by this investigation, a capacitance electrode comprising W (tungsten) film and so forth, is formed on the region, and the capacitance is formed virtually, and failure analysis is carried out while judging whether the failure level degrades or not by the LSI tester.
However, the above failure analysis method has the following problems. The first problem is that the engineer in a mass-production plant is able to determine whether it is a timing failure or not but it is difficult for the engineer to identify the failure portion region and implement the subsequent failure analysis. This is because in order to presume a failure portion of the semiconductor integrated circuit based on the test pattern in which failure occurs, expertise both on the circuit and on the test patterns and circuit operations is essential.
The second problem is that it is extremely difficult to put up a probe needle on the wiring after a hole is provided using lasers and so forth, on the passivation film on the failure portion of the semiconductor integrated circuit based on the test pattern generating the failure. This is because the wiring width and distance between wirings of the semiconductor integrated circuit are less than 1 .mu.m as refinement of elements further proceeds.
The third problem is that time for forming the W film takes 1 to 2 hours per region when the electrode such as W film and so forth, is provided on the region after identifying the failure portion. Consequently, to form the capacitance at several portions, for example, more than 8 hours are required. This is because the apparatus such as FIB (focused ion beam) or FLB (focused laser beam) used for forming the W film is a vacuum apparatus and needs time for evacuation. In addition, the difficulty of specifying the region for forming the capacitance causes the time for forming the W film to take long. As a result, one to two hours are required for forming the W film per region.